Silicon carbide (SiC) devices characterized by high efficiency, high power density and wide bandgap, have great potential in many advanced applications, such as electric automotive, aviation and military. Thermal management, condition monitoring and life estimation of SiC modules are essential to achieve high reliability. These control techniques require real-time monitoring or estimation of the module's junction temperature. This paper proposed a thermal model based on an integrated negative thermal coefficient (NTC) thermistor in SiC modules. The Finite Element Methods simulation results showed that the parameters of the thermal model are invariant under different heat dissipation conditions and ambient temperatures. The combination of the proposed thermal model with the reading of NTC sensor realized the online estimation of the junction temperature. The accuracy of the thermal model and the independence of thermal impedance were verified by simulation and experimental results.

Inductors realized with high permeable MnZn ferrite require, unlike iron-powder cores with an inherent distributed gap, a discrete air gap in the magnetic circuit to prevent saturation of the core material and/or tune the inductance value. This large discrete gap can be divided into several partial gaps in order to reduce the air gap stray field and consequently the proximity losses in the winding. The multi-gap core, realized by stacking several thin ferrite plates and inserting a non-magnetic spacer material between the plates, however, exhibits a substantial increase in core losses which cannot be explained from the intrinsic properties of the ferrite. In this paper, a comprehensive overview of the scientific literature regarding machining induced core losses in ferrite, dating back to the early 1970s, is provided which suggests that the observed excess core losses could be attributed to a deterioration of ferrite properties in the surface layer of the plates caused by mechanical stress exerted during machining. However, in a first experimental analysis no structural evidence for a deteriorated layer close to the surface is identified by means of Scanning Electron Microscopy (SEM). Therefore, in a next step, a new calorimetric measurement setup based on temperature rise monitoring is proposed in this paper in order to quantify and differentiate between core losses associated with the bulk and the surface of the ferrite plates and therefore to pinpoint the measured excess core loss to shallow layers of ferrite with deteriorated magnetic performance. Electrical measurement of the surface related core losses utilizing the widely accepted two-winding wattmeter method with reactive power compensation is outlined in the appendix but was not employed in this work due to comparably low measurement accuracy. By means of the proposed measurement technique, the bulk and surface core loss density of the MnZn ferrite material 3F4 from FerroxCube was determined for sinusoidal flux density amplitude varying from 75 mT up to 200 mT and excitation frequencies ranging from 200 kHz to 1 MHz. The measured core loss densities (W/cm³) show good agreement with the Steinmetz model provided by the manufacturer validating the proposed calorimetric core loss measurement technique. The measured surface loss density (W/cm²) can also be well predicted with a Steinmetz model, whereby the frequency exponent α in the surface is slightly smaller and the flux density exponent β is slightly larger compared to the Steinmetz parameter of the bulk ferrite. It is shown that the ratio between surface and bulk core losses of a composite core assembled from individual plates is only a function of plate thickness and does not depend on the actual cross section area. Critical plate thickness is then defined to be reached when the total power loss in the composite core has doubled compared to a solid (single-piece) core sample. This new quantity provides a very helpful figure for multi-gap inductor designs. Besides the deteriorated surface layers, several other mechanisms potentially contributing to increased core losses in multi-gap inductors were identified and are finally discussed in the appendix of this paper: flux crowding in the core due to tolerances and imperfections in machining and assembly; deterioration of ferrite properties due to pressure buildup in the stack of plates during the curing of the employed epoxy resin; ohmic loss in the ferrite associated with the current flowing in the conduction path provided by the low impedance of the ferrite material at high frequencies and the parasitic capacitance between winding and the ferrite core.

Switched reluctance machines receive increased attention from the automotive industry because of their cost efficiency. However, the independent phase excitation and the resulting current reversal demand comparatively large dc-link capacitors to meet the requirements regarding the ripple on the dc-link voltage and current. This paper validates the effects of the usage of a dc-dc boost converter to reduce the size of the dc-link capacitor by actively filtering the source current. The active filter is compared with the state-of-the-art topology and a passive filter. The investigations show that the active filter is able to reduce the dc-link capacitance by 80%. The dc-dc converter also provides the feature of adjusting the inverter dc-link voltage level independently from the battery voltage level. The positive effect of this additional degree of freedom on the machine efficiency is investigated and due to this feature the total efficiency of the electrical drive train remains nearly unchanged despite the extra losses in the dc-dc converter. All presented results are based on detailed simulations and experimentally validated with a 20 kW switched reluctance generator.

With the increasing use of photovoltaic systems, a large demand for efficient, power-dense and lightweight grid-interface inverters is arising. Accordingly, new concepts like multi-level converters, which are able to reduce the converter losses while still keeping a low construction volume, have to be investigated. The hybrid seven-level topology analyzed in this paper comprises an active neutral point clamped stage, followed by a flying capacitor stage. Compared to a pure flying capacitor converter, the combination of these two stages allows to save more than half of the capacitor volume, while still having the same requirement for the output filter stage, and hence, the same output filter volume. Moreover, the topology employs low-voltage devices and ensures low conduction and switching losses, resulting in a higher efficiency. The principle of operation of the system is briefly reviewed, and based on a detailed component modeling, an efficiency vs. power density optimization is carried out, for which switching loss measurements of state-of-the-art 200 V semiconductors are performed. From the optimization, a high-efficiency design is selected and the practical hardware realization is discussed. The simulation and optimization results are then verified by realizing an all-silicon 99.35% efficient three-phase seven-level system, featuring a volumetric power density of 3.4 kW/dm³ (55.9 W/in³), a gravimetric power density of 3.2 kW/kg, and fulfilling CISPR Class A EMI requirements. Finally, it is shown that an all-silicon realization with next generation silicon switches can achieve 99.5% efficiency with the same hardware, and 99.6% with commercial state-of-the-art GaN switches.

Transient instability events of grid-tied converters probably occur while riding through grid faults. During low-voltage ride through (LVRT) period, seeing from the converter terminal towards the grid, the Thévenin equivalent grid impedance becomes pretty significant, accordingly making the converter terminal voltage highly sensitive to the output current. Under such circumstances, it is challenging for the converter to resynchronize with the grid via a phase-locked loop (PLL). This paper develops a reduced-order nonlinear model to elaborate on the dynamic synchronization characteristic of the converters. By considering the impact of grid impedance and analysing spatial vector tracking relation, resynchronization principle of the converters during LVRT is revealed. Besides, the impacts of circuit parameters and controller parameters, including residual grid voltage, grid impedance, current references, and PLL parameters, on the transient stability of the converters are investigated. The results are verified by simulation and experimental results.

In this paper, a new single-stage single-phase isolated AC-DC converter derived from a differential boost AC-DC converter is proposed. This converter eliminates the need to use the bulky electrolytic capacitor from the system and at the same time provides DC charging by employing the AC Power Decoupling waveform control method, effectively addressing the power density and reliability related issues commonly associated with the bulky electrolytic capacitor. As half of the switches of this converter act as synchronous rectifier during half grid cycle, they are inherently ZVS Turned On while the remaining switches achieve ZVS Turn On as they act as synchronous rectifier during other half grid cycle. However, all diodes at the secondary side achieve ZCS Turn Off during the entire line cycle. A conventional controller is implemented for output voltage regulation and PFC control whereas a power decoupling controller is added to compensate second harmonic ripple power. Besides, an interleaving technique is applied to provide high-frequency links for transformers’ connection while at the same time increasing the power range and effectively reducing the size of the input filter. Finally, the operating principle of the converter is validated through simulation, and the experimental results are provided.

In this paper, a network-based approach to model capacitive wireless power transfer systems is introduced. The modeling methodology provides insights into the electrical cross-coupling relationships between input and output parameters of the capacitive power transfer (CPT) systems, including the effect of distance and alignment of the coupling plates. It is revealed that, regardless of the circuit complexity or matching network order, the model core can be reduced to a basic gyrator relationship with added coefficients when required, thus obtaining a compact, closed-form relationship between the input and output terminals. The model has been validated through rigorous simulations and experiments; all found to be in excellent agreement with the theoretical predictions under changes of the air-gap, and medium capacitance. To this end, an experimental CPT prototype that operates in the MHz range has been designed and implemented while the transmitter and receiver have been realized by four 170 mm × 170 mm copper plates. In addition, to provide better insight into the capacitive interface under different structures and distances and alignments, the capacitive coupler has been methodically examined through Finite Elements Analysis (FEA) tools Maxwell (Ansys). The results of the FEA have been utilized in the simulation platform to enhance the accuracy of the simulations, accounting for the variable capacitance under variations.

This paper introduces two types of single-stage high-frequency isolated converters named isolated modular multilevel converter (I-M2C) and isolated modular cascaded converter (I-MC2), which are both based on the high-frequency-link concept. The two converters can totally reduce the individual DC-link capacitors at the high-voltage (HV) side and simplify the voltage balancing control. The fundamental principle and applied modulation strategy scheme of I-M2C and I-MC2 are given in details. The operation mode of I-M2C is analysed as an example. Experimental results are given respectively to illustrate the efficient operating characteristics of the two new types of converters.

Fundamental frequency sorting algorithm (FFSA) is outstanding for the MMC capacitor voltage balance due to the reduced computational burden and elimination of arm current detection. However, with the traditional carrier-phase-shifted pulse width modulation (CPS-PWM) scheme, FFSA will be ineffective when the carrier frequency is higher than 250 Hz, where the line frequency is 50 Hz. Thus, previous works proposed a logic-processed CPS-PWM scheme to overcome this disadvantage. This paper furtherly introduces the application ranges and implementation of this logic-processed CPS-PWM scheme based capacitor voltage balancing method in detail. With a detailed mathematical analysis, the factors that influence the balancing strategy’s convergence speed are obtained, i.e., modulation index and power factor angle. It is found that in the applications where the modulation index is usually higher than 0.75, the influence of the modulation index is negligible. However, when the power factor angle is closed to ±π/2, the convergence speed is almost zero. Therefore, by comparing with the traditional CPS-PWM scheme based FFSA balancing method, the application ranges of power factor angle are revealed to guarantee a high convergence speed. Meanwhile, the balancing strategy’s application scope is specified. Moreover, a three-tier control architecture is demonstrated, where the logic process of driving signals and capacitor voltage sorting process are both executed in the middle-tier FPGA controller. This centralized scheme guarantees the synchronization of switching actions. And the logic process is easy and cost-effective in FPGA. Simulation and experimental results are presented to validate the theoretical analysis.