Fundamental frequency sorting algorithm(FFSA) is outstanding for the MMC capacitor voltage balance due to the reduced computational burden and elimination of arm current detection. However, with the traditional carrier-phase-shifted pulse width modulation(CPS-PWM) scheme, FFSA will be ineffective when the carrier frequency is higher than 250 Hz, where the line frequency is 50 Hz. Thus, previous works proposed a logic-processed CPS-PWM scheme to overcome this disadvantage. This paper furtherly introduces the application ranges and implementation of this logic-processed CPS-PWM scheme based capacitor voltage balancing method in detail. With a detailed mathematical analysis, the factors that influence the balancing strategy’s convergence speed are obtained, i.e., modulation index and power factor angle. It is found that in the applications where the modulation index is usually higher than 0.75, the influence of the modulation index is negligible. However, when the power factor angle is closed to ±π/2, the convergence speed is almost zero. Therefore, by comparing with the traditional CPS-PWM scheme based FFSA balancing method, the application ranges of power factor angle are revealed to guarantee a high convergence speed. Meanwhile, the balancing strategy’s application scope is specified. Moreover, a three-tier control architecture is demonstrated, where the logic process of driving signals and capacitor voltage sorting process are both executed in the middle-tier FPGA controller. This centralized scheme guarantees the synchronization of switching actions. And the logic process is easy and cost-effective in FPGA. Simulation and experimental results are presented to validate the theoretical analysis.