The existing discrete SiC MOSFETs still use traditional soldering packaging technology for Si devices. However, SiC material has a higher coefficient of thermal expansion, which means that the solder layer of SiC MOSFETs bears greater thermal stress, making it more prone to aging and failure at the same current level. In this paper, a press-pack (PP) method for optimizing the thermal performance and reliability of discrete SiC MOSFETs is proposed. Firstly, a PP package for discrete SiC MOSFET is raised. Secondly, the thermal performance of the same SiC MOSFET chip in the designed PP structure and commonly used TO-247-3 structure is compared based on COMSOL Multiphysics simulation. Finally, the power cycle test platform for discrete SiC MOSFETs is built and the reliability of the designed PP structure is verified. The research results show that the PP structure has the advantage of optimizing the thermal performance and reliability of the discrete SiC MOSFETs.