This paper presents a finite control set model predictive control (FCS-MPC) strategy for three-phase three-level T-type off-grid inverters, with the aim of optimizing current tracking performance. First, the voltage vector function range and the subsector regions are redefined with the integration of the voltage vector synthesis concept, which helps reduce current ripples and thus total harmonic distortions. Then, to promote neutral point potential balance, a time compensation mechanism is introduced, complementing the passive balance through voltage vector synthesis. To address the issue of high computational complexity, a two-step sector determination strategy is proposed. The proposed FCS-MPC is both tested through simulation and experiment. Compared with the conventional approach, the proposed strategy shows superior results in terms of algorithm execution time, neutral potential balance, steady-state performance, and dynamic response.

The CLLC converter offers advantages such as high efficiency, high power density, bidirectional Buck-Boost capability, and soft-switching operation, and has been widely applied in automotive onboard chargers and renewable energy systems. Electromagnetic compatibility (EMC) is one of the critical performance indicators for CLLC circuits. To investigate the conducted common-mode (CM) EMI characteristics of the CLLC converter, a CM EMI equivalent circuit model was established based on the noise transmission mechanism, and an equivalent model of the CLLC converter was derived, clarifying the noise source characteristics and the key CM noise transmission path impedances. The noise source characteristics under different operating conditions were analyzed to reveal the CM noise behavior in each condition. Based on this analysis, a symmetry-based design method for optimizing the CM EMI performance of the CLLC converter was proposed, and the impacts of resonant inductor and capacitor symmetry were examined. The correctness of the CM characteristic analysis for the CLLC converter is verified through simulations and experimental tests. By constructing a symmetric resonant cavity structure, the CM noise is attenuated by 20–30 dB, which further validates the feasibility of the symmetric structure-based optimization design method.

For open-end winding induction motor (OEWIM) fed by dual three-level inverters, traditional model predictive current control (MPCC) suffers from issues such as excessive vector enumeration, complex control algorithm design, and slow dynamic response. This paper proposes a low voltage jump single-phase independent model predictive current control (LVJ-SPI-MPCC) method. Firstly, by establishing a single-phase independent predictive current model, the independent prediction and optimization of the switching states for each phase leg are achieved, reducing the number of optimal switching state selections per control cycle from 729 to 27. Secondly, to suppress phase voltage jumps, a switching state selection rule based on a voltage jump constraint is proposed, constructing a collaborative optimization strategy for low voltage jump and single-phase independent control. This limits the phase voltage jump within the range of ±U/2 and further reduces the predictive computations per cycle to 15. Finally, the effectiveness of the proposed method is verified based on MATLAB/Simulink simulations and the Typhoon HIL 402 experimental platform. Experimental results show that the proposed method significantly reduces the computational burden and improves the system’s dynamic response speed while ensuring control accuracy.

Abstract—Due to the increasing switching speed of the widely [6]. It is more difficult to achieve high bandwidth for current band gap (WBG) devices, there is an urgent demand for the high-bandwidth current sensor. However, the low bandwidth of the low-resistance coaxial current shunt (CCS) becomes the hindrance to the WBG device characterizations. This paper proposes a low-cost bandwidth compensation method for the low-resistance CCS. Since the structure of the CCS is complicated, it is regarded as a two-port network, and a high-resistance high-bandwidth CCS is used to generate the compensation transfer function. The proposed method is verified by the double pulse test (DPT) of a Gallium Nitride (GaN) device. The maximum errors for the turn-on switching loss and total switching loss after compensation are 1.1% and 1.2%, respectively. While these values before compensations are 35.3% and 31.7%, respectively. In addition, the proposed method is not sensitive to the preselected testing condition, which indicates its high practical engineering value. Index Terms—Coaxial current shunt resistor, current measurement, GaN device, high bandwidth.

PHOTOVOLATIC power generation has become one of the key technologies promoting the low-carbon transformation of energy due to its advantages such as no pollution, no noise, and flexible distributed deployment [1], [2]. The centralized architecture of PV power station adopts a modular series-parallel approach to form a PV array, and realizes DC-AC power conversion and grid connection through grid-connected inverters. The structure is simple and the inverter efficiency is relatively high, but the system expansion and redundancy capabilities are poor [3]. The multi-branch architecture is equipped with independent DC-DC converter in each branch of the PV array. This flexibility of the PV grid-connected system. Even when a single DC/DC converter fails, the system can still operate stably. However, it has problems such as rising hardware costs and the persistence of series faults of PV modules [4]. With the rapid development of PV power generation systems towards large capacity and high voltage, the problem of fault protection on the DC side has become increasingly prominent. Especially DC arc faults, due to their strong concealment, high the primary hidden danger threatening the safe operation of PV systems [5], [6]. According to the analysis of fault mechanisms, DC arc faults are mainly divided into series arc faults and parallel arc faults. Parallel arcs are usually caused by insulation breakdown due to aging of wires or equipment [7], [8]. Series faults are induced by poor contact, aging of lines, or environmental factors, and their fault characteristics are more complex and occur more frequently [9], [10]. Scholars mechanism, fault detection and fault protection. The occurrence mechanism of arc is the basis for further theoretical analysis [11], [12] and simulation tests [13], [14]. Regarding the mechanism research of DC arc, literature [11] established an arc fault model for PV systems, systematically analyzed the fault generation mechanism, and analyzed the DC characteristics based on the voltage and current waveform features. [12] discussed the use of actual data recorded in the PV system to drive an effective DC series arc model from the original Nottingham arc model. This model has three parameters, including a current index constant, model order, and two time series coefficients. [13] proposed a heuristic average model based on the principle of arc power balance and provided a current-controlled arc noise simulation method based on the correlation mechanism between arc noise and arc current. By superimposing arc noise on the proposed average model, the dynamic characteristics of DC series arc can be accurately described. [14] modeled the physical characteristics of arcs in photovoltaic (PV) systems. The simulations were carried out with ANSYS Fluent and ANSYS Maxwell in the ANSYS software. The results contributed to the standardization

With the large-scale integration of renewable energy into modern power systems, grid-forming (GFM)-based inverters will play an increasingly important role. Currently, the design approach for the AC-side inductance of filter in GFM inverters still follows that of grid-following (GFL)-based inverters, potentially hindering optimal performance. To tackle this issue, an optimized design method for the AC-side inductance of GFM inverters is proposed in this paper by taking into account the specific requirements of various applications. Furthermore, a customized parameter design method for the AC-side inductance is introduced, aiming to achieve a balance between dynamic performance needs and control challenges. Finally, the validation of the proposed optimized design method is demonstrated through simulations and experimental results obtained from the Modeling Tech StarSim controller hardware-in-the-loop platform.

This paper presents a new single-phase, switched-capacitor-based five-level inverter with double voltage gain, designed for renewable energy applications. The topology utilizes switched capacitors (SCs) alongside a simple T-type converter and a half-bridge circuit with self-voltage balancing capability, eliminating the need for additional sensors to balance the capacitors. Furthermore, a midpoint clamping neutral is incorporated to reduce leakage current and common-mode voltage, making it particularly suitable for photovoltaic applications. A simple proportional-resonant (PR) controller is employed for grid current control, while a straightforward level-shifted pulse-width modulation (LS-PWM) technique generates the five-level output voltage waveform using two carrier signals, simplifying control complexity. An experimental setup is developed to validate the effectiveness of the proposed topology with R and RL loads under both steady-state and dynamic conditions, as well as grid-tied operation. Capacitor voltage balancing and the effect of the modulation index are also presented. Moreover, a hardware-in-the-loop (HIL) cosimulation is performed for grid control using Xilinx System Generator blocks in the MATLAB/Simulink environment, with the results provided. Additionally, a comprehensive comparison highlights the advantages of the proposed topology compared to recent solutions reported in the literature.

This paper addresses the challenges of automatically designing low-inductance, compact three-level SiC power modules. The graph-based layout design automation method has the merit of seeking all possible solutions but may result in a significant calculation burden when considering complex mutual-inductance influences. To overcome this limitation, an efficient analytical method is developed to calculate parasitic inductance with mutual-inductance effects considered. Comparisons with numerical and experimental results prove the efficacy and accuracy of the proposed analytical method. A graph-based layout automation approach is developed, enabling multi-objective optimization of parasitic inductance and module footprint by incorporating mutual inductance. The method is applied to a three-level SiC module featuring six chips (four MOSFETs and two diodes). Pareto front solutions are analyzed to identify optimal trade-offs between inductance and compactness, demonstrating the effectiveness of the proposed methodology in enhancing design efficiency and performance for high-efficiency power electronics applications.

Load-side asynchronous motors (AMs) inherently lower rotor speeds during frequency dips, reducing active power absorption and delivering vital inertial support. However, existing frequency regulation strategies overlook the dual objectives, neglecting frequency response adaptability and induction motor operational stability. This paper proposes a segmented rate of change of frequency (ROCOF) control strategy for AM-based primary frequency regulation. First, ROCOF is divided into distinct intervals. In low ROCOF regions, AMs leverage natural electromechanical transients to stabilize frequency. In medium-high ROCOF regions, coordinated control AMs, which incorporate with variable-frequency asynchronous motors (VFAMs) using adaptive droop coefficients are deployed. This coordination maximizes frequency support while maintaining VFAMs’ stability. An adaptive model predictive control (MPC) framework is then designed to optimize dynamic frequency tracking for VFAMs. Simulations and hardware-in-the-loop (HIL) validate the strategy under uncertain system disturbances. Compared to conventional methods, the proposed approach elevates frequency nadirs, confirming enhanced transient performance, while maintaining normal operating conditions.

The rapid scaling of accelerated computing is pushing rack power well beyond 1 MW, making conventional 48 V distribution increasingly inefficient due to busbar and connector currents. High-voltage DC (HVDC) distribution (e.g., 800 V) enables lower distribution losses and motivates server boards that interface directly to an HVDC bus. This paper addresses two enabling building blocks on the server board: (i) safe hot-swap and eFuse functionality with controlled pre-charging and telemetry, and (ii) high-power-density conversion from 800 V to intermediate-bus voltages. For hot-swap, a 1200 V-rated SiC JFET cascode is evaluated in linear mode and demonstrated to pre-charge 300 μF from 0 V to 800 V in approximately 1.5 s while staying within the device SOA limits. For power conversion, an unregulated LLC-DCX approach is investigated. An 800 V-to-50 V input-series-output-parallel (ISOP) half-bridge converter using GaN switches on the primary and secondary side and a matrix transformer reaches 98.1% efficiency at full load and a peak efficiency above 98.4%. A direct 800 V-to-12 V converter prototype achieves 97% at 6 kW and 98.2% peak efficiency.