Busbars integrate conductors, insulation, and terminals, facilitating the seamless connection of capacitors, power devices, and other components. A well-engineered busbar design minimizes parasitic elements, which is crucial for maintaining stable system performance. This article combines SiC MOSFET power modules, Si IGBT power modules, and discrete Si IGBT devices. By employing an optimization strategy, it refines the placement of components, the laminate sequencing, the positioning of terminals and capacitors to reduce the parasitic parameters of the current commutation loop(CCL), leading to an enhanced PCB laminated busbar design. To improve current-carrying capacity between the inner and outer PCB layers while minimizing inductance, via-in-pad technology is utilized. According to Q3D simulation, the parasitic inductance of the large CCLs are reduced to just 58.93nH and 59.39nH.