In this paper, a new substrate layout is proposed in order to mitigate the short-circuit current imbalance of a typical multi-chip power module with paralleled SiC MOSFETs. Compared with the typical SiC power modules, the influence of common-source inductance mismatch on the current imbalance is effectively minimized in the proposed layout. Consequently, the current sharing performance of the paralleled SiC MOSFETs in the multi-chip power module is improved. The analyses are verified by simulation and experimental results, which further validate the effectiveness of this mitigating method.