In 10 kV medium-voltage distribution networks, higher electric field strengths demand more stringent insulation. Merely increasing the insulation layer thickness of busbar can lead to excessive parasitic inductance, degraded switching performance, significant switching losses and electromagnetic interference, particularly in high-frequency applications. This paper utilizes finite element simulation to optimize insulation for an ANPC converter using 15 kV SiC MOSFETs and proposes a partial discharge (PD) free optimization strategy. The thickness of the final PCB busbar is only 6.09 mm, and partial discharge test as well as insulation resistance tests are conducted at +8 kV/-8 kV voltage. The results show that this design exhibits symmetrical parasitic parameters, low commutation loop inductance, and high insulation capability. The optimized design ensures efficient and reliable operation of high-voltage converters, meeting the stringent requirements for modern power electronics applications.