This paper reports a research of the ESD robustness of GaN HEMT power devices with p-GaN gate structure. We investigated the positive short-pulse stress on the gate as well as the negative one. Transmission line pulse (TLP) was used in combination to generate the stress in this experiment. From the experiments, we found that such a structure has a stable performance under positive stresses on the gate. But the devices turn to be unstable when negative ones are applied, observed from the reduction of output current, transconductance maximum value and positive shift of threshold voltage. These phenomena, may be caused by the traps in the p-GaN layer, is an important reference for static protection designs of the p-GaN devices.