A fast electro-thermal simulation strategy for SiC power MOSFETs is presented in this paper. This approach features the detailed mapping of the device power losses under a wide range of operating conditions by using a compact electrical model and its experimental validation for a 1.2 kV/36 A commercial device. The losses condition map is used in the simplified model of a half-bridge inverter topology. The average device losses per switching period are injected into a multi-layer thermal impedance network obtained via finite-element method (FEM) simulation. The strategy allows the electro-thermal simulation of a simple switching pattern in a very short time (seconds), compared to an equivalent physically-based circuit simulation, without significant accuracy loss, enabling long-timescale simulation and reliable, mission-profile oriented design of power electronic converters.