In this work, a GaN vertical super-junction (SJ) MOSFET with trench gate is proposed and studied by TCAD simulation. In order to achieve the typical electric field (E-field) modulation effect by the P+/N+/N+ structure in the conventional Si SJ-MOS, the P-GaN/UID-GaN/N+-GaN stack is alternatively used by taking into account the unavailability of P+-GaN. In this manner, the P-GaN and N+-substrate serve as the field-stop (FS) layers in the proposed GaN SJ-MOS. In reverse bias, the breakdown of the device is governed by two mechanisms: 1) the punch-through in the top P-GaN/N-drift junction due to the possible under design of the P-GaN thickness; 2) the avalanche breakdown triggered by high E-field due to the possible under design of the bottom UID-GaN thickness. Hence, from the uniform E-field distribution point of view, a device optimization approach for GaN vertical SJ-MOS is proposed. The hole and electron density of P-GaN and N-drift are optimized to achieve a uniform E-field distribution in the device both in lateral and vertical directions, which is found to be 6×10^16 cm^-3. Moreover, the thickness ratio of P-GaN/UID-GaN is designed to obtain an identical intrinsic breakdown for the top P-GaN/N-drift junction and bottom UID/N-drift region, which enables the maximum Baliga’s figure-of-merit of the device. The concept of device design and optimization is of great interest for GaN vertical devices for over kilovolts applications.